This invention relates generally to computer organization and more particularly to register file organization in a computer architecture having a large number of registers or multiple functional units.
A typical multiported register file 10 is shown in FIG. 1. The register file 10 includes N registers each having M read ports and at least one write port. Coupled to the register file 10 are instruction decoders 12 which decode instructions held in a number L of instruction registers 14. Typically there are two read ports for each instruction register, i.e., M=2.times.L, to allow both source operands to be fetched simultaneously. The plurality of registers 14 include L registers, with each register being associated with a corresponding functional unit (not shown). This organization is typical for a superscalar architecture or a very long word instruction word (VLIW) architecture, wherein each instruction register 14 is associated with a corresponding functional unit. The decoders 12 decode the register fields of the instruction registers 14 and select the corresponding register in the register file 10. Also coupled to the register file 10 are a plurality of registers 16. Each of the registers 16 is coupled to a respective one of the output ports or read ports of the register file 10.
A detailed schematic of an individual register cell 18 of the register file 10 is shown in FIG. 2. The cell 18 includes two inverters I1 and I2 connected in a circular fashion to form the basis of the register cell. The register cell of FIG. 2 includes two read ports (P1 and P2) and a single write port (W). The write port includes pass transistor 20 connected between a write bit line Bit Line W and an input of the register cell. The first read port includes transistors 22 and 26 and the second read port includes transistors 24 and 25, each port being connected in a conventional manner, as is known in the art. It is apparent that with the addition of each read port the size of the register cell increases. This increased size of the register cell increases the access time of the overall register file due to the increase in capacitance and resistance of the individual cells. This problem is exacerbated if the number of registers in the register file is relatively large as well because of the increased capacitance and resistance of the bit lines in the register file. In fact, it can be shown that the access time is a quadratic function of the number of functional units and the number of registers.
Simulations of the register file of FIGS. 1 and 2 demonstrate the relationship of the access time of the register file as a function of the number of functional units and the number of registers in the register file. The results of these simulations are shown in FIG. 3. In FIG. 3, the access time of the register file Taccess is plotted as a function of the number of functional units for a number of different sized register files. The access time as a function of the number of functional units for register files having 32, 64, 128, 192 and 256 is shown in plots 32, 34, 36, 38 and 40, respectively, in FIG. 3.
Although the access time of the register file (Taccess) is typically not the critical path of the microprocessor, as the number of functional units and/or number of registers increases, the access time of the register file can become the critical path of the microprocessor. For example, assuming a critical path of two nanoseconds, for a register file having 128 registers, a computer architecture having over four functional units will result in the register file becoming the critical path in the computer. This relationship is shown in plot 36 of FIG. 3. Although current superscalar architectures typically do not require more than four functional units, VLIW architectures are capable of supporting significantly more functional units than four. As a result, the access time the register file in VLIW architectures can be a significant obstacle to achieving very fast cycle times.
Accordingly, a need remains for a low access time register file for a computer architecture having multiple functional units.